The present invention relates generally to phase detectors for phase lock loops, and more specifically to a sample-hold phase detector which generates a ramp voltage proportional to a phase difference between two input signals and samples and holds the ramp voltage to produce a phase detectpr output.
According to the prior art sample-hold phase detector, a "ramp" capacitor is charged for an interval corresponding to a phase difference between an input signal and a reference signal to develop a ramp voltage proportional to the phase difference. A sample-and-hold circuit is connected to the ramp capacitor to sample and hold the ramp voltage in response to a sampling pulse. With the recent tendency toward LSI implementation of electronic circuitry, it is desirable to fabricate all components of the sample-and-hold circuit on a single LSI chip. However, the value of the storage capacitor of the sample-and-hold circuit cannot be made sufficiently large to prevent the applied sampling pulse from bypassing the "sample" switch of the sample-and-hold circuit by way of the parasitic capacitance of the switch, to the storage capacitor. Therefore, the phase detector output contains an undesirable ripple voltage which occurs at the same frequency as the reference signal.